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1 wideband differential 3:1 multiplexer isl54233 the intersil isl54233 is a single supply differential 3 to 1 multiplexer that operates from a single supply in the range of 2.7v to 4.6v. it was designed to multiplex between three different differential data source s, allowing the multiplexing of usb 2.0 high speed data signals, uart data signals and digital video through a common headphone connector in personal media players and other portable battery powered devices. the switch channels have low on capacitance and high bandwidth (1.6ghz) to pass usb high speed signals (480mbps) and digital video signals with minimal edge and phase distortion and can swing rail-to-rail to pass uart and full-speed usb signals. all channels of the multiplexer can be turned off (disabled) by driving the c0 and c1 logic pins to the low state. the isl54233 is available in a tiny 12 ld 2.2mmx1.4mm ultra-thin qfn and 12 ld 3mmx3m m tqfn package. it operates over a temperature range of -40c to +85c. related literature ? technical brief tb363 ?guidelines for handling and processing moisture sensitive surface mount devices (smds)? features ? high speed (480mbps) and fu ll speed (12mbps) signaling capability per usb 2.0 on all ports ? digital video transmission ? com pins allow negative swings to -2v ? all switches off mode ? power off protection ? com pins overvoltage tolerant to 5.5v ? low on capacitance @ 240mhz . . . . . . . . . . . . . . . . . . 2.8pf ? -3db frequency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.6ghz ? single supply operation (v dd ) . . . . . . . . . . . . . . . . 2.7v to 4.6v ? available 12 ld utqfn and 12 ld tqfn packages ? compliant with usb 2.0 short circuit requirements without additional external components ? pb-free (rohs compliant) applications ? mp4 and other personal media players ? mobile phone/smart phone ? tablets, readers, gps and mhl figure 1. typical application figure 2. bandwidth characteristics curve isl54233 digital video uart usb/data jack com - com + c1 gnd 1d+ 1d- 2d+ 2d- vdd c0 logic controller v bus 3.3v 3d- usb 4m ? transceiver 3d+ 1m 10m 100m 1g 2g frequency (hz) normalized gain (db) -4 -3 -2 -1 0 1 v in = 0dbm, 0.86vdc bias r l = 50 ? december 21, 2011 fn7918.0 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas inc. 2011. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners.
isl54233 2 fn7918.0 december 21, 2011 pin configuration 12 ld 2.2x1.4 utqfn top view 12 ld 3x3 tqfn top view note: 1. isl54233 switches shown for c1 = logic ?1? and c0 = logic ?0?. 10 12 9 c1 com - com + v dd c0 8 7 11 6 4 5 2 1 3 3d+ 2d- 2d+ gnd 1d- 1d+ 3d- logic control 4m ? 4m ? 1 3 12 c1 com - com + v dd c0 11 10 2 9 7 8 5 46 3d+ 2d- 2d+ gnd 1d- 1d+ 3d- logic control 4m ? 4m ? pd pin descriptions utqfn tqfn name function 1 1 3d+ usb3/dv differential input 2 2 2d- usb2/dv differential input 3 3 2d+ usb2/dv differential input 4 4 1d- usb1/dv differential input 5 5 1d+ usb1/dv differential input 6 6 gnd ground connection 7 7 com+ data common pin 8 8 com- data common pin 9 9 c1 digital control input 10 10 c0 digital control input 11 11 v dd power supply 12 12 3d- usb3/dv differential input - pad pad thermal pad. tie to ground or float truth table c1 c0 mode comments 0 0 wired-or audio all switches open 0 1 usb/dv #1 1d- and 1d+ on 1 0 usb/dv #2 2d- and 2d+ on 1 1 usb/dv #3 3d- and 3d+ on c0, c1: logic ?0? when 0.5v or float, logic ?1? when 1.4v with v dd in range of 2.7v to 3.6v.
isl54233 3 fn7918.0 december 21, 2011 ordering information part number part marking temp. range (c) package (pb-free) pkg. dwg. # isl54233iruz-t (notes 2, 3) hm -40 to +85 12 ld 2.2mmx1.4mm utqfn (tape and reel) l12.2.2x1.4a isl54233iruz-t7a (notes 2, 3) hm -40 to +85 12 ld 2.2mmx1.4mm utqfn (tape and reel) (250pc reel) l12.2.2x1.4a ISL54233IRTZ (note 4) 4233 -40 to +85 12 ld 3mmx3mm tqfn l12.3x3a ISL54233IRTZ-t (note 2, 4) 4233 -40 to +85 12 ld 3mmx3mm tqfn (tape and reel) l12.3x3a notes: 2. please refer to tb347 for details on reel specifications. 3. these intersil pb-free plastic packaged products employ specia l pb-free material sets; molding compounds/die attach materials and nipdau plate - e4 termination finish, which is rohs compliant and compat ible with both snpb and pb-free soldering operations. intersil pb-free products are msl classified at pb-free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. 4. these intersil pb-free plastic packaged products employ spec ial pb-free material sets, molding compounds/die attach materials , and 100% matte tin plate plus anneal (e3 termination finish , which is rohs compliant and compatible wi th both snpb and pb-free soldering opera tions). intersil pb-free products are msl classified at pb-fr ee peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jed ec j std-020. 5. for moisture sensitivity level (msl), please see device information page for isl54233 . for more information on msl please see techbrief tb363 .
isl54233 4 fn7918.0 december 21, 2011 absolute maximum rating s thermal information v dd to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 5.5v input voltages 1d+, 1d-, 2d+, 2d-, 3d+, 3d- . . . . . . . . . . . . . . . . . . . . . . . . . . -2v to 5.5v c0, c1 (note 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 5.5v output voltages com-, com+ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2v to 5.5v continuous current (1d-, 1d+, 2d-, 2d+, 3d-, 3d+). . . . . . . . . . . . . . . . . 40ma peak current (1d-, 1d+, 2d-, 2d+, 3d-, 3d+) (pulsed 1ms, 10% duty cycle, max) . . . . . . . . . . . . . . . . . . . . . . 100ma esd rating: human body model (tested per jesd22-a114f) . . . . . . . . . . . . . . . >5kv machine model (tested per jesd22-a115b) . . . . . . . . . . . . . . . . . >400v charged device model (tested per jesd22-c110d) . . . . . . . . . . . . >2kv latch-up (tested per jesd-78b; class 2, level a) . . . . . . . . . . . . . . . . . at +85c thermal resistance (typical) ja (c/w) jc (c/w) 12 ld utqfn package (notes 7, 10) . . . . . 155 90 12 ld tqfn package (notes 8, 9) . . . . . . . 58 1.0 maximum junction temperature (plastic package) . . . . . . . . . . . +150c maximum storage temperature range . . . . . . . . . . . . . . . . . -65c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/ pbfree/pb-freereflow.asp operating conditions temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40c to +85c supply voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7v to 4.6v caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 6. signals on c1 and c0 exceeding gnd by specified amount are clamped. limit current to maximum current ratings. 7. ja is measured with the component mounted on a high effective thermal conductivity test board in free air. see tech brief tb379 for details. 8. ja is measured in free air with the componen t mounted on a high effective thermal conduc tivity test board with ?direct attach? fe atures. see tech brief tb379 . 9. for jc , the ?case temp? location is the center of the exposed metal pad on the package underside. 10. for jc , the ?case temp? location is taken at the package top center. electrical specifications - 2.7v to 3.6v supply test conditions: v dd = +3.0v, gnd = 0v, v c0h , v c1h = 1.4v, v c0l , v c1l =0.5v, (note 11), unless otherwise specified. boldface limits apply ov er the operating temperature range, -40c to +85c. parameter test conditions temp (c) min (notes 12, 13) typ max (notes 12, 13) units analog switch characteristics analog signal range, v analog v dd = 2.7v to 4.6v full -1 - v dd v on-resistance, r on v dd = 2.7v, i comx = 17ma, v d+ or v d- = 0v to 400mv (see figure 5, note 15) 25 - 6 8 ? full - - 10 ? r on matching between channels, r on v dd = 2.7v, i comx = 17ma, v d+ or v d- =voltage at max r on , (notes 15, 16) 25 - 0.07 0.5 ? full - - 0.55 ? r on flatness, r flat(on) v dd = 2.7v, i comx = 17ma, v d+ or v d- = 0v to 400mv, (notes 14, 15) 25 - 0.32 0.8 ? full - - 1.2 ? on-resistance, r on v dd = 3.3v, i comx = 17ma, v d+ or v d- = 3.3v (see figure 5, note 15) +25 - 9.5 15 ? full - - 20 ? off leakage current, i xd+(off) or i xd-(off) , i comx(off) v dd = 4.6v, all off mode (c0 = 0.5v, c1 = 0.5v), v com- or v com+ = 0.3v, 3.3v, v xd+ or v xd- = 3.3v, 0.3v 25 -15 - 15 na full -20 - 20 na on leakage current, i xd+(on) or i xd-(on) , i comx(on) v dd = 4.6v, v xd+ or v xd- = 0.3v, 3.3v, v com- or v com+ = 0.3v, 3.3v 25 -20 - 20 na full -25 - 25 na dpdt dynamic characteristics all off to on or on to all off address transition time, t trans v dd = 2.7v, r l = 50 , c l = 10pf, (see figure 3) 25 - 125 - ns data channel to data channel address transition time, t trans v dd = 2.7v, r l = 50 , c l = 10pf, (see figure 3) 25 - 125 - ns break-before-make time delay, t d v dd = 3.6v, r l = 50 , c l = 10pf, (see figure 4) 25 - 30 - ns skew, (t skewout - t skewin ) v dd = 3.0v, r l = 45 , c l = 10pf, t r = t f = 500ps at 480mbps, (duty cycle = 50%) (see figure 8) 25 - 75 - ps total jitter, t j v dd = 3.0v, r l = 50 , c l = 10pf, t r = t f = 500ps at 480mbps 25 - 210 - ps
isl54233 5 fn7918.0 december 21, 2011 rise/fall degradation (propagation delay), t pd v dd = 3.0v, r l = 45 , c l = 10pf, ( see figure 8) 25 - 250 - ps crosstalk v dd = 3.0v, r l = 50 , f = 240mhz 25 - -36 - db off-isolation v dd = 3.0v, r l = 50 , f = 240mhz 25 - -32 - db -3db bandwidth signal = 0dbm, 0.2vdc offset, r l = 50 25 - 1.6 - ghz off capacitance, c xd+off , c xd-off f = 1mhz, v dd = 3.0v (see figure 6) 25 - 3 - pf com on capacitance, c com-(on) , c com+(on) f = 1mhz, v dd = 3.0v (see figure 6) 25 - 6 - pf com on capacitance, c com-(on) , c com+(on) f = 240mhz, v dd = 3.0v 25 - 2.8 - pf power supply characteristics power supply range, v dd full 2.7 4.6 v positive supply current, i dd (all off mode) v dd = 3.6v, c1 = gnd, c0 = gnd 25 - 6.5 8 a full - - 15 a positive supply current, i dd (usb1 mode) v dd = 3.6v, c1 = gnd, c0 = v dd 25 - 6.5 8 a full - - 15 a positive supply current, i dd (usb2 mode) v dd = 3.6v, c1 = v dd , c0 = gnd 25 - 6.5 8 a full - - 15 a positive supply current, i dd (usb3 mode) v dd = 3.6v, c0 = c1 = v dd 25 - 6.5 8 a full - - 15 a power off comx current, i comx v dd = 0v, c0 = c1 = float, comx = 5.25v 25 - - 1 a power off logic current, i c0 , i c1 v dd = 0v, c0 = c1 = 5.25v 25 - 11 - a power off d+/d- current, i xd+ , i xd- v dd = 0v, c0 = c1 = float, xd- = xd+ = 5.25v 25 - 5 - a digital input characteristics c0, c1 voltage low, v c0l , v c1l v dd = 2.7v to 3.6v full - - 0.5 v c0, c1 voltage high, v c0h , v c1h v dd = 2.7v to 3.6v full 1.4 - 5.25 v c0, c1 input current, i c0l , i c1l v dd = 3.6v, c0 = c1 = 0v or float full -50 6.2 50 na c0, c1 input current, i c0h , i c1h v dd = 3.6v, c0 = c1 = 3.6v full -2 1.6 2 a c0, c1 pull-down resistor, r cx v dd = 3.6v, c0 = c1 = 3.6v, measure current into c0 or c1 pin and calculate resistance value. full - 4 - m notes: 11. v logic = input voltage to perform proper function. 12. the algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. 13. parameters with min and/or max limits are 100% tested at +25c , unless otherwise specified. te mperature limits established b y characterization and are not production tested. 14. flatness is defined as the difference between maximum and mini mum value of on-resistance over the specified analog signal ra nge. 15. limits established by characteriza tion and are not production tested. 16. r on matching between channels is calculated by subtracting the channel with the highest max r on value from the channel with lowest max r on value, between 1d+ and 1d- or between 2d + and 2d- or between 3d+ and 3d-. electrical specifications - 2.7v to 3.6v supply test conditions: v dd = +3.0v, gnd = 0v, v c0h , v c1h = 1.4v, v c0l , v c1l =0.5v, (note 11), unless otherwise specified. boldface limits apply ov er the operating temperature range, -40c to +85c. (continued) parameter test conditions temp (c) min (notes 12, 13) typ max (notes 12, 13) units
isl54233 6 fn7918.0 december 21, 2011 test circuits and waveforms logic input waveform is inverted for switches that have the opposite logic sense. figure 3a. address t trans measurement points repeat test for all switches. c l includes fixture and stray capacitance. figure 3b. address t trans test circuit figure 3. switching times figure 4a. measurement points repeat test for all switches. c l includes fixture and stray capacitance. figure 4b. test circuit figure 4. break-before-make time figure 5. r on test circuit figure 6. capacitance test circuit 50% t r < 20ns t f < 20ns t off 90% v c0,c1 0v v input v c0,c1 t on logic input switch input switch output 90% v out v out v (input) r l r l r on + ----------------------- - = switch input logic v out r l c l comx c0, c1 50 10pf gnd v dd c v input input 90% v c0 v c1 t d logic input switch output 0v v out logic c0, c1 comx r l c l v out 10pf 50 2d- or 2d+ 1d- or 1d+ v dd gnd v input c input 3d- or 3d+ v dd c 0v xd- or xd+ comx c0 gnd v d- or v d+ v 1 r on = v 1 /17ma 17ma repeat test for all switches. c1 v dd v dd c gnd xd- or xd+ comx v cx impedance analyzer v cxl or repeat test for all switches. ctrl v cxh
isl54233 7 fn7918.0 december 21, 2011 figure 7. crosstalk test circuit figure 8a. measurement points figure 8b. test circuit figure 8. skew test test circuits and waveforms (continued) 0v or float analyzer v dd c xd- signal generator 50 ? gnd v cx comx 50 ? n.c. comx xd+ ctrl din+ din- out+ out- 50% 50% 90% 10% 10% 10% 10% 90% 90% 50% 90% 50% t ri t fi t ro t f0 t skew_i t skew_o out+ c l com- d+ gnd v dd c d- com+ c l out- din+ din- |tro - tri| delay due to switch for rising input and rising output signals |tfo - tfi| delay due to switch for falling input and falling output signals |tskew_0| change in skew through the switch for output signals |tskew_i| change in skew through the switch for input signals 15.8 ? 15.8 ? 143 ? 143 ? 45 ? 45 ? c0 c1 v dd v dd 0v
isl54233 8 fn7918.0 december 21, 2011 application block diagram detailed description the isl54233 device consists of dual sp3t (single pole/triple throw) analog switches. it oper ates from a single dc power supply in the range of 2.7v to 4.6v . it was designed to function as a differential 3 to 1 multiplexer to select between three different differential data signals. it is offered in tiny utqfn and tqfn packages for use in mp3 players, pdas, cellphones, and other personal media players. the device consists of six 6 ? data switches. it was designed to pass high-speed usb differential data and digital video signals with minimal edge and phase distortion. it can swing rail-to-rail to pass uart and full-speed usb signals. the com pins can accept signals that swing below ground by as much as -2v. this allows an audio source to be wired-or connected at the com pins. the isl54233 was specifically designed for mp3 players, personal media players and cellpho ne applications that need to combine three differential data channels into a single shared connector, thereby saving space and component cost. this functionality is shown in the typical application block diagram on page 1. a detailed description of the switch es is provided in the following sections. data switches the six data switches (1d+, 1d-, 2d+, 2d-, 3d+, 3d-) are 6 ? bidirectional switches that were specifically designed to pass high-speed usb differential data signals in the range of 0v to 400mv. the switches have low capacitance and high bandwidth to pass usb high-speed signals (480mbps) with minimum edge and phase distortion to meet usb 2.0 signal quality specifications. see figures 15 and 16 for high-speed eye pattern taken with the switch in the signal path. these switches can also swing ra il-to-rail and pass usb full-speed (12mbps) and uart signals with minimal distortion. see figure 17 for usb full-speed eye pattern taken with the switch in the signal path. the maximum normal operatin g signal range for the usb switches is from -1v to v dd . the signal voltage at d- and d+ should not be allowed to exceed the v dd voltage rail or go below ground by more than -1 v for normal operation. fault protection and power-off protection however, in the event that the usb 5.25v v bus voltage were shorted to one or both of the com pins, the isl54233 has fault protection circuitry to prevent damage to the isl54233 part. the fault circuitry allows the signal pins (com-, com+, 1d-, 1d+, 2d-, 2d+, 3d-, 3d+) to be driven up to 5.25v while the v dd supply voltage is in the range of 0v to 4.6v. this fault condition causes no stress to the ic. in addition, when v dd is at 0v (ground) all switches are off and the fault voltage is isolated from the other side of the switch (power-off protection). when v dd is in the range of 2.7v to 4.6v, the fault voltage will pass through to the output of an active switch channel. note: during the fault conditio n, normal operation is not guaranteed until the fault condition is removed. isl54233 operation the discussion that follows will discuss using the isl54233 in the ?application block diagram? on page 8. isl54233 digital video uart usb/data jack com - com + c1 gnd 1d+ 1d- 2d+ 2d- vdd c0 logic control controller vbus 3.3v 3d- usb 4m ? transceiver 3d+ audio codec isl54406 head phone jack 100 ?
isl54233 9 fn7918.0 december 21, 2011 power the power supply connected at v dd (pin 11) provides power to the isl54233 part. its voltage should be kept in the range of 2.7v to 4.6v. in a typical application, v dd will be in the range of 2.7v to 4.3v and will be connected to the battery or ldo of the mp3 player or cellphone. a 0.01f or 0.1f decoupling capacitor should be connected from the v dd pin to ground to filter out any power supply noise from entering the part. the capacitor should be located as close to the v dd pin as possible. logic control the state of the isl54233 device is determined by the voltage at the c1 pin (pin 9) and the c0 pin (pin 10). refer to the ?truth table? on page 2. the c1 pin and c0 pin are internally pulled low through 4m resistors to ground and can be tri-stated or left floating. the c1 pin and c0 pin can be driven with a voltage that is higher than the v dd supply voltage. they can be driven up to 5.25v with the v dd supply in the range of 2.7v to 4.6v. driving the logic higher than the supply rail will cause the logic current to increase. with v dd = 2.7v and v logic = 5.25v, i logic current is approximately 5.5a. logic control voltage levels with v dd in the range of 2.7v to 3.6v the logic levels are: c1, c0 = logic ?0? (low) when 0.5v or floating. c1, c0 = logic ?1? (high) when 1.4v. all switches off mode if the c1 pin = logic ?0? and c0 pi n = logic ?0? the part will be in the all switches off mode. in this mode, the 3d- and 3d+ data switches, the 2d- and 2d+ data switches, and the 1d- and 1d+ data switches will be off (high impedance). the com pins can accommodat e signals that swing below ground by as much as -2v. this allows an audio codec to be connected to the com pins when the device is in the all off state. usb/dv 1 mode if the c1 pin = logic ?0? and c0 pin = logic ?1? the part will go into usb/dv1 mode. the 1d- and 1d+ switches are on and the 2d- and 2d+ switches and 3d- and 3d+ will be off (high impedance). usb/dv 2 mode if the c1 = logic ?1? and c0 pin = logic ?0? the part will be in the usb/dv2 mode. the 2d- and 2d+ sw itches will be on and the 1d- and 1d+ switches and the 3d- and 3d+ will be off (high impedance). usb/dv 3 mode if the c1 pin = logic ?1? and c0 pi n = logic ?1? the part will be in the usb/dv3 mode. the 3d- and 3d+ switches are on, and the 1d- and 1d+ switches and 2d- an d 2d+ switches will be off (high impedance). printed circuit board design for high frequency performance in 50 ? systems, the isl54233 has a -3db bandwidth of 1.6ghz (see figure 19). to achieve this high bandwidth requires careful design and layout of the pcb board. signal traces must be designed to minimize reflections and reduce parasitic resistance, inductance and capacitance that degrade the frequency response performance. figure 9 shows a picture of the engineering board used to measure the frequency response of the isl54233 part. the board was specifically design for taking high frequency bandwidth measurements. the board was made with special materials and was carefully layed out using rf board techniques to maximize it for high frequency operation. the next section, ?board layout guidelines?, will provide a list of the pcb board requirements needed to get the maximum bandwidth from the isl54233 part when tested with a 50 network analyzer. figure 9. rf high frequency board
isl54233 10 fn7918.0 december 21, 2011 board layout guidelines ? the isl54233 device must be soldered directly onto the pcb board. no ic sockets ca n be used. their parasitic impedance will degrade the frequency performance. ? the signal traces (1d+, 1d-, 2d+, 2d-, 3d+, 3d-, com- and com+) must have a controlled (characteristic) impedance of 50 ? 5% . tight control on trace width and dielectric thickness must be followed to get 50 ? lines. impedance tests results for controlled line s should be requested from the board fabrication house. ? a four layer pcb board: signal (top) layer), thin-dielectric, gnd (2nd layer), thick-diel ectric, gnd (3rd layer), thin-dielectric, signal (bottom layer) is required to achieve 50 ? traces. the top and bottom thin-dielectric are nelco 4000-13 or rogers 4350 core type material. the center thick-dielectric is fr4 pre-preg material. figure 10 illustrates the material and sequencing of the layers. the dimensions called out are those required to achieve 50 ? microstrip for the signal traces. ? route all controlled impedance signal lines on the top (signal) layer with no vias or through holes. vias or through holes make it difficult to maintain a controlled impedance and tend to generate reflections. ? the signal trace lengths should be as short ( <1 inch from sma connector to the switch pi n) and straight as possible. if it becomes necessary to turn 90, use two 45 turns or an arc instead of making a single 90 turn. this reduces reflections on the signal by minimizing impedance discontinuities. ? use edge - launch sma connectors for all signal lines. the sma connector terminal should be tapered to the signal trace. ? ground stitching should be do ne along signal traces and around sma ground connectors. this helps to isolate the trace in a ground conduit. this reduces capacitive coupling between traces and provides a good return path for the signal. ? use dry film solder mask. clea r the solder mask from signal trace. ? power and/or logic lines can be run on the bottom layer. logic lines should be routed aw ay from the signal lines. this will minimize capacitive coupling from the logic lines. ? a 4.7f capacitor is placed from v cc to gnd where the power is brought onto the board. it keeps any low frequency noise from getting on the board. since a bulk capacitor will look inductive at higher frequencies, an additional 0.1f capacitor is placed across the supply lines. a 0.01f decoupling capacitor needs to be connected from the v dd pin to ground of the isl54233 part to filter out any power supply noise from entering the part. the capacitor should be a rf type chip capacitor and should be located as close to the v dd pin as possible. note: rf type capacitors have a smaller foot-print than regular capacitors. figure 10. four layer board stack-up top (signal) layer gnd layer fr4 pre-preg gnd layer bottom layer 5 mil 52 mil 5 mil 10 mil rogers 4350 core rogers 4350 core trace gnd gnd
isl54233 11 fn7918.0 december 21, 2011 typical performance curves t a = +25c, unless otherwise specified. figure 11. on-resistance vs supply voltage vs switch voltage figure 12. on-resistance vs switch voltage vs temperature figure 13. on-resistance vs switch voltage vs temperature f igure 14. on-resistance vs switch voltage vs temperature 5.8 5.9 6.0 6.1 6.2 6.3 6.4 6.5 6.6 6.7 0 0.050.100.150.200.250.300.35 0.40 r on ( ? ) v com (v) i com = 40ma v dd = 2.7v v dd = 3.0v v dd = 3.3v v dd = 4.0v v dd = 4.6v v dd = 3.6v 3 4 5 6 7 8 9 0 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 r on ( ? ) v com (v) +85c -40c i com = 40ma +25c v dd = 2.7v 3 4 5 6 7 8 9 0 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 r on ( ? ) v com (v) +85c +25c -40c v dd = 3.3v i com = 40ma 2 4 6 8 10 12 14 16 0 0.5 1.0 1.5 2.0 2.5 3.0 3.3 +25c r on ( ? ) v com (v) +85c -40c v dd = 3.3v i com = 40ma
isl54233 12 fn7918.0 december 21, 2011 figure 15. eye pattern: 480mbps with usb switches in the signal path typical performance curves t a = +25c, unless otherwise specified. (continued) time scale (0.2ns/div) voltage scale (0.1v/div) v dd = 2.7v usb near end mask
isl54233 13 fn7918.0 december 21, 2011 figure 16. eye pattern: 480mbps with usb switches in the signal path typical performance curves t a = +25c, unless otherwise specified. (continued) time scale (0.2ns/div) voltage scale (0.1v/div) v dd = 2.7v usb far end mask
isl54233 14 fn7918.0 december 21, 2011 figure 17. eye pattern: 12mbps usb signal with usb switches in the signal path typical performance curves t a = +25c, unless otherwise specified. (continued) time scale (10ns/div) voltage scale (0.5v/div) v dd = 2.7v
isl54233 15 fn7918.0 december 21, 2011 figure 18. off-isolation usb switches figure 19. frequency response die characteristics substrate and tqfn thermal pad potential (powered up): gnd transistor count: 837 process: submicron cmos typical performance curves t a = +25c, unless otherwise specified. (continued) frequency (hz) normalized gain (db) 0.001 0.01 0.1 1m 10m 100m 500m -140 -120 -100 -80 -60 -40 -20 v in = 0.2v p-p to 2v p-p r l = 50 ? 1m 10m 100m 1g 2g frequency (hz) normalized gain (db) -4 -3 -2 -1 0 1 v in = 0dbm, 0.86vdc bias r l = 50 ?
isl54233 16 intersil products are manufactured, assembled and tested utilizing iso9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn7918.0 december 21, 2011 for additional products, see www.intersil.com/product_tree products intersil corporation is a leader in the design and manufacture of high-performance analog semico nductors. the company's product s address some of the industry's fastest growing markets, such as , flat panel displays, cell phones, handheld products, and noteb ooks. intersil's product families address power management and analog signal processing functions. go to www.intersil.com/products for a complete list of intersil product families. for a complete listing of applications, rela ted documentation and related parts, please see the respective device information p age on intersil.com: isl54233 to report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff fits are available from our website at http://rel.intersil.com/reports/search.php revision history date revision change december 21, 2011 fn7918.0 initial release.
isl54233 17 fn7918.0 december 21, 2011 package outline drawing l12.3x3a 12 lead thin quad flat no lead plastic package rev 0, 09/07 located within the zone indicated. the pin #1 indentifier may be unless otherwise specified, tolerance : decimal 0.05 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 identifier is optional, but must be between 0.18mm and 0.30mm from the terminal tip. dimension b applies to the metallized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing conform to amse y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: bottom view detail "x" side view typical recommended land pattern top view (4x) 0.15 index area pin 1 a 3.00 b 3.00 6 1 3 7 9 4 6 10 12 pin #1 index area 12x 0 . 4 0 . 1 b 0.10 ma c 4 6 0.25 +0.05 / -0.07 0 . 5 4x 1.45 bsc ( 2 . 8 typ ) ( 1.45 ) 0 . 25 0 . 50 0 . 6 0 . 75 c seating plane base plane 0.08 0.10 see detail "x" c c 0 . 00 min. 0 . 05 max. 0 . 2 ref c 5
isl54233 18 fn7918.0 december 21, 2011 ultra thin quad flat no-lead plastic package (utqfn) 6 b e a d 0.10 c 2x index area 2 1 n nx (b) section "c-c" e cc 5 c l terminal tip (a1) l 0.10 c 2x c 0.05 c a 0.10 c a1 leads coplanarity 0.10 m c a b 0.05 m c pin #1 id 5 (datum b) (datum a) nx l nd ne 3 e nx b 12 bottom view side view top view l12.2.2x1.4a 12 lead ultra thin quad flat no-lead plastic package symbol millimeters notes min nominal max a 0.45 0.50 0.55 - a1 - - 0.05 - a3 0.127 ref - b 0.15 0.20 0.25 5 d 2.15 2.20 2.25 - e 1.35 1.40 1.45 - e 0.40 bsc - k0.20- - - l 0.35 0.40 0.45 - n122 nd 3 3 ne 3 3 0-124 rev. 0 12/06 notes: 1. dimensioning and tolerancing conform to asme y14.5-1994. 2. n is the number of terminals. 3. nd and ne refer to the number of terminals on d and e side, re- spectively. 4. all dimensions are in millimeters. angles are in degrees. 5. dimension b applies to the meta llized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. the pin #1 identifier may be ei- ther a mold or mark feature. 7. maximum package warpage is 0.05mm. 8. maximum allowable burrs is 0.076mm in all directions. 9. same as jedec mo-255uabd except: no lead-pull-back, "a" min dimension = 0.45 not 0.50mm "l" max dimension = 0.45 not 0.42mm. 10. for additional information, to assist with the pcb land pattern design effort, see intersil technical brief tb389. 10 2.30 0.40 0.45 (12x) 1.50 1 2 3 0.25 (12x) 0.40 typical recommended land pattern

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